Company has reported net profit after tax of Rs 1.73 Crore in latest quarter.The company’s top management includes Mr.Makrand M Appalwar, Mrs.Rinku Appalwar, Mr.Krishnan I Subramanian, Mr.Nitin D ...

We have ported ref design ZCU102 to ZCU104 FPGA (Vivado 23.1). The simulation works fine as per TI-JESD204-IP: Simulation of loopback design in Vivado - Data converters forum - Data converters - TI ...

I have a DAC followed by voltage feedback amp LM6172 in an existing design which is driving a 20 Khz signal with capacitive load of around 60 pF. I need to update the design to drive 400 pF at 25 Mhz.

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