Design-Reuse4 年
DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency
The DDR IP is compliant with the latest JEDEC standards and is silicon proven. This memory controller supports DDR4, DDR3, DDR3L, LPDDR4 SDRAM. This memory controller is a high-speed interface used ...
Design-Reuse2 年
DDR3L/ LPDDR4/ DDR4 PHY IP - 1866Mbps (Silicon Proven in UMC 28HPC+)
The DDR3L/ DDR4/ LPDDR4 Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the UMC 28HPC+ process technology, complies with the most recent ...